This disclosure relates generally to optoelectronic devices and more particularly to a light emitting diode (LED) die, and to a method for fabricating the light emitting diode (LED) die.
A light emitting diode (LED) die can include a multi layer semiconductor substrate made of a compound semiconductor material, such as GaN. For example, the semiconductor substrate can include a p-type confinement layer having p-type dopants, an n-type confinement layer having n-type dopants, and a multiple quantum well (MQW) layer located between the confinement layers configured to emit electromagnetic radiation. A light emitting diode (LED) die also includes an n-electrode and a p-electrode for making external connections to the outside world. With a vertical light emitting diode (VLED), the semiconductor substrate is located between the n-electrode and the p-electrode, which are vertically separated. With a horizontal light emitting diode (LED) die, the n-electrode and the p-electrode are still separated on the semiconductor substrate but are generally planar to one another.
With either type of die, at least one of the electrodes can block and absorb electromagnetic emission from the multiple quantum well (MQW) layer, thus decreasing electroluminescence intensity. For example, with a vertical light emitting diode (VLED) die, the n-electrode can be located on the n-type confinement layer directly in the path of electromagnetic radiation emitted by the multiple quantum well (MQW) layer. Because of this absorption, it is necessary to make the surface of the n-electrode as small as possible. However, the structure and the morphology of the vertical light emitting diode (VLED) die can make the n-electrode larger. For example, one type of vertical light emitting diode (VLED) die includes light extraction structures, such as roughened elements on the n-type confinement layer.
The n-electrode, which is formed in close proximity to these roughened extraction structures, can also have an increased surface area which blocks emission and lessens the benefit of the extraction structures. This situation is illustrated in FIG. 1. A prior art vertical light emitting diode (VLED) die 10 includes an n-type confinement layer 12 in electrical contact with an n-electrode 14, a multiple quantum well (MQW) layer 16 configured to emit electromagnetic radiation, and a P-type confinement layer/reflector 18 in electrical contact with a p-electrode 20. In addition, the n-type confinement layer 12 includes light extraction structures 24 in the form of multi faceted elements that provide light scattering. However, as indicated by the circled area 22 in FIG. 1, the n-electrode 14 has an increased surface area due to deposition of metal on the light extraction structures 24.
Another problem is that during fabrication of the n-electrode 14, a loading effect can occur, which decreases the roughness of the extraction structures 24 and their effectiveness. For example, as shown in FIG. 2, during the fabrication process for the vertical light emitting diode (VLED) die 10, a mask 26 can be used to protect the area where the metal for the n-electrode 14 (FIG. 1) will be deposited. However, as indicated by the circled area 28 in FIG. 2, the mask 26 can have a loading effect in which the roughness of the light extraction structures 24 decreases along the edges of the mask 26. Further, due to limitations in photolithography tolerances, it is difficult to form the electrodes 14 without adversely affecting the light extraction structures 24.
One proposed solution for these problems would be to form the n-electrode 14 directly on the light extraction structures 24. However, direct deposition on the light extraction structures 24 can form the n-electrode 14 with a rough surface, which is known to cause higher electrical resistivities in deposited electrodes and conductors. In addition, the roughed surface of the n-electrode 14 can cause a high contact resistance to outside electrical connections (e.g., wire bonds). Higher contact resistances between the n-electrode 14 and the n-type confinement layer 12 can also occur due to a low dopant level in the n-type confinement layer 12. However, a low dopant level is required to reduce film defects in a MOCVD process for forming the n-electrode 14.
The present disclosure is directed to a light emitting diode (LED) die having light extractions structures and at least one electrode with a small surface area for minimizing absorption of electromagnetic radiation, but with a high electrical conductivity, a low contact resistance and a planar morphology. Also provided are a method for fabricating the light emitting diode (LED) die and a light emitting diode (LED) system incorporating the die.